comp.sys.acorn (1785/1796) Path: cix!slxsys!ukc!acorn!osmith From: osmith@acorn.co.uk (Owen Smith) Newsgroups: comp.sys.acorn Subject: Re: Hardware support (was Re: Risc-OS Documentation) Message-ID: <9191@acorn.co.uk> Date: 15 Aug 91 15:06:13 GMT References: <1991Aug14.165349.12313@vaxa.strath.ac.uk> Sender: osmith@acorn.co.uk Distribution: comp Organization: Acorn Computers Ltd, Cambridge, England Lines: 236 In article <1991Aug14.165349.12313@vaxa.strath.ac.uk>, cabr07@vaxa.strath.ac.uk writes: >The A540 has a VIDC enhancer built in which is supported in Risc OS 2.01 >fixing the sound frequency shift problem. Is the A540 enhancer wired up >in the same way that upgrades for older machines are - so would Risc OS >2.01 in an old machine fix the sound when used with an enhancer? It will indeed fix the sound pitch. You need a bit more code though. The A540 VIDC clocks are not wired up the same as the AtomWide Turbo VIDC. However, what you can do is write a small module which sits on Service_ModeChange, and whenever the mode changes reads the VIDC clock speed (new VDU variable - number 172). This gets you the speed the kernel wants in KHz. You then have to broddle the hardware that you have appropriately. The kernel knows about 24000, 25175 and 36000 KHz. So if you get 25175 (VGA modes) you'll have to settle for using 24000. Secondly you need your modes to declare what pixel rate they should use. If you leave the AtomWide MegaModes module in, it will fight with the kernel. If you select say Mode 102, MegaModes will broddle the VIDC up to 36 MHz, but the kernel will think it should be running at 24 MHz so the speed change module will turn it back down again. Brian Brunswick (Brian.Brunswick@cl.cam.ac.uk) has a fixed Taxan795 MegaModes module which I'm sure he'd be prepared to let people have. Here is the documentation for declaring the pixel rate for your mode: Additions to the mode extension system for A540 and similar machines ==================================================================== This document describes extensions to the RISC OS mode extension system for machines which have programmable VIDC clock speeds and sync polarities, such as the A540. Familiarity with the RISC OS 2.00 mode extension system is assumed (this is described in the existing Programmer's Reference Manual). The A540 has extra hardware to allow the selection of different VIDC clocks and to determine the polarity of the sync lines. VIDC uses its clock together with a set of internal dividers to provide a range of pixel rates. The format of the "VIDC list" returned from Service_ModeExtension (&50) has been extended to allow the pixel rate and sync polarities to be specified. On original Archimedes machines, the VIDC clock is fixed at 24MHz, and the pixel rate is only determined by VIDC's internal dividers, as specified in bits 0 and 1 of the Control Register (VIDC address &E0). This would be stored in the VIDC list as a word of the form &E00000xx. RISC OS now supports two different format VIDC lists. The original (type 0) VIDC list format is as follows:- Offset Value 0 0 4 VIDC base mode 8 VIDC parameter 12 VIDC parameter .. .. n -1 The new (type 1) VIDC list format is as follows:- Offset Value 0 1 4 VIDC base mode 8 VIDC parameter 12 VIDC parameter .. .. n -1 n+4 Extended parameter n+8 Extended parameter .. .. m -1 where extended parameters are of the form (0 << 24) + (pixel rate in kHz) or (1 << 24) + (sync polarity) The sync polarity is defined as follows:- bit 0 = 0 => HSync +ve (as on a standard Archimedes) = 1 => HSync -ve bit 1 = 0 => VSync +ve (as on a standard Archimedes) = 1 => Vsync -ve bits 2..23 must be zero A pixel rate specifier in a type 1 VIDC list will override the settings of bits 0 and 1 of a Control Register specifier in the main body of the list. If no pixel rate is specified, then the VIDC clock is set to 24MHz, and the settings of the divider in the Control Register are used as normal. The A540 hardware provides the following pixel rates:- 24000 kHz, 25175 kHz, 36000 kHz with a multiplier of 2/2 16000 kHz, 16783 kHz, 24000 kHz with a multiplier of 2/3 12000 kHz, 12587 kHz, 18000 kHz with a multiplier of 1/2 8000 kHz, 8392 kHz, 12000 kHz with a multiplier of 1/3 If the pixel rate specified is not achievable with the hardware on the machine, the nearest available pixel rate is used. Note: when specifying a pixel rate for a hi-res-mono display, the pixel rate specified should be the actual pixel rate divided by 4, ie 24000 not 96000. If no sync polarity is specified, a default of 0 is used (ie the same as a normal Archimedes). --------------------------------------------------------------------------- And here is my source code for a module to turn an AtomWide Turbo VIDC speed up and down. It's in AAsm format and it uses loads of header files, but I'm sure you'll get the basic idea. It shouldn't be too hard to change for other VIDCs. Also I heard there are two versions of the AtomWide board, one of which has the polarity of the control line inverted ie. when you switch your machine on it runs at 36 MHz! Of course I could post the binary for the module to comp.binaries.acorn, but then the chances of it actually getting out past the black hole are almost zero. ; > VIDCClock ; Change List ; 24 Apr 91 0.01 OSS Module created. ; 14 May 91 0.02 OSS Made input list static data - smaller and faster. ; 07 Jul 91 0.03 OSS Changed name from VIDCSupprt to VIDCClock. ; -------------------------------------------------------------------------- GET Hdr:ListOpts GET Hdr:Macros GET Hdr:System GET Hdr:ModHand GET Hdr:Services GET Hdr:Proc GET Hdr:VduExt GET Hdr:NewSpace ; -------------------------------------------------------------------------- module_base DCD 0 ; No start entry DCD init_entry - module_base ; Initialisation entry DCD 0 ; No die entry DCD service_entry - module_base ; Service entry DCD title_string - module_base ; Title string DCD help_string - module_base ; Help string DCD 0 ; No * commands DCD 0 ; No SWI chunk ; -------------------------------------------------------------------------- help_string DCB "VIDC Clock", 9, "0.03 (03 Jul 1991)" DCB " for AtomWide Turbo VIDC", 0 ; -------------------------------------------------------------------------- title_string DCB "VIDCClock", 0 ; -------------------------------------------------------------------------- service_entry ROUT TEQ r1, #Service_ModeChange TEQNE r1, #Service_Reset ; Not actually necessary. MOVNE pc, lr ; Some other service call. ; ** Drop through ** init_entry ENTRY "r0-r1", 4 ; 4 bytes of stack. ADR r0, vidc_clock_speed_list ; Input list is static data. MOV r1, sp ; Output list is on stack. SWI XOS_ReadVduVariables EXIT VS LDR r1, [sp] ; Get speed (25175 etc.). LDR r0, =30000 CMP r1, r0 MOVHS r0, #1 ; If >= 30000, go for 36MHz. MOVLO r0, #0 ; Otherwise, go for 24 MHz. BL atomwide_on_off EXIT vidc_clock_speed_list DCD VduExt_VIDCClockSpeed DCD -1 ; -------------------------------------------------------------------------- ; Just because I am paranoid, a couple of assertions to make sure that things ; don't move around. Admittedly LatchB is unlikely to move (it's hardware!) ; but someone might take it into their heads to move the soft copy for some ; strange reason. Of course, if there was a SWI to read/write LatchB there ; wouldn't be a problem. ASSERT LatchBSoftCopy = &105 ASSERT LatchB = &03350018 ; -------------------------------------------------------------------------- ; Entry: r0 = 0 Set clock speed to 24 MHz ; r0 = 1 Set clock speed to 36 MHz ; Exit: All registers preserved atomwide_on_off ENTRY "r0-r5" LDR r3, =LatchBSoftCopy ; Zero page location LDR r4, =LatchB ; Address for speed selection MOV r2, pc ORR r1, r2, #(I_bit :OR: F_bit) TEQP r1, #0 ; Disable IRQs and FIQs LDRB r5, [r3, #0] ; Get zero page soft copy BIC r5, r5, #&20 ; Clear existing bit value ORR r5, r5, r0, LSL #5 ; Set bit for on/off STRB r5, [r3, #0] ; Store zero page soft copy STRB r5, [r4, #0] ; Write new LatchB setting TEQP r2, #0 ; Restore IRQ and FIQ status EXIT ; -------------------------------------------------------------------------- END The views expressed are my own and are not necessarily those of Acorn.