A Series Podules ~~~~~~~~~~~~~~~~ Name: 0310101 Version: 0.02 History: 0.01: Undated : started. 0.02: 15-Feb-89: updated for release on SID Notes ~~~~~ ____ 1. Any reference to an inverted signal such as IOGT will be given in the text as bar IOGT. 2. This document makes reference to 24 figures. These will be found in the DRAWINGS directory. 1. Introduction 1.1 General 1.2 Physical Dimensions 1.2.1 Fitting a Podule 1.3 Types of Podule 1.3.1 Simple Podules 1.3.2 MEMC Podules 1.3.3 Coprocessor Podules 1.3.4 External Podules 2. The I/O System for ARM Based Computers 2.1 System Architecture 2.1.1 non-IOC devices 2.2 System Memory Map 2.3 I/O Space Memory Map 2.4 Podule Access Speed 2.4.1 Simple Podules 2.4.2 External Podules 2.4.3 MEMC Podules 2.5 Podule Size 2.6 Data Bus Mapping 2.6.1 Byte Accesses 2.6.2 Half-Word Accesses 2.6.3 Word Accesses 2.7 Podule Interrupt Handling 2.8 Podule Identification 3. The Potule Bus 3.1 Simple Podule and MEMC Podule Interface 3.2 Coprocessor Podule Interface 3.3 Main PCB Connector 3.4 Loading of the Podule Bus 3.5 Signal Standards 3.6 Power Requirements 4. Podule Identity 4>1 Podule Identity Space 4.1.1 Code Space 4.2 Podule Identity Low Byte 4.2.1 Podule Presence 4.2.2 Podule Interrupts 4.2.3 ID field 4.2.4 Acorn Discriminator 4.3 Identification Extension 4.3.1 FIQ and IRQ Status 4.3.2 Country Code 4.3.3 Manufacturer Code 4.3.4 Product Type Code 4.4 Interrupt Status Pointers 4.5 Chunk Directory Structure 4.5.1 Operating System Identity Byte 4.6 Examples of Use 4.6.1 Non-extended Podule Identity 4.6.2 Extended Podule Identity 4.6.3 Extended PI with paged ROM 5. Simple Podules 5.1 Podule Accesses 5.1.1 slow cycle read 5.1.2 slow cycle write 5.1.3 medium cycle read 5.1.4 medium cycle write 5.1.5 fast cycle read 5.1.6 fast cycle write 5.2 General Timing For Slow, Medium and Fast Cycle Types 5.3 synchronous cycle read 5.4 synchronous cycle write 5.5 Timings for Synchronous Cycle Type 6. MEMC Podules 6.1 I/O Controller Interface 6.2 MEMC Podule Timing 1 Introduction ============== 1.1 General ----------- A Podule is the general expansion mechanism for ARM based computer systems. This specification defines the physical and electrical standards of the Podule system, and the operating system independent parts of the software interface. It is assumed that the reader is familiar with the basic concepts of the ARM based computer systems. Reference should be made to ARM, MEMC and IOC data sheets. In general, Podules are PCBs to the Eurocard standard which plug into a backplane inside the machine. The backplane in turn plugs into the main computer PCB. Each Podule has an integral backpanel which gives provision for connectors to the outside world. Podules normally have a 64 way DIN 41612ac connector, with the a and c rows loaded. In addition, a Coprocessor Podule requires the b row to be loaded; the interface for a Coprocessor Podule is a 96 way DIN 41612abc connector. The Archimedes 300 series will require a backplane and fan (Acorn Sales Code AKA01) to be fitted before any Podules can be installed. The Archimedes 300 series backplane has two sockets and does not have the necessary connections to allow the use of Coprocessor Podules. The Archimedes 400 series has a four socket backplane fitted as standard and a Coprocessor Podule can be used. 1.2 Physical Dimensions ----------------------- Podules are constructed to the Eurocard specification and are mounted horizontally. Podules may be either single or double width (ie height in the normal Eurocard specification). Podules are 5HP (1") high. A double width Podule, when viewed from above with the external connectors towards you, should have its Podule connector fitted in the left-hand position. Note: On early Archimedes 300 and 400 series the distance between the backplane and the inner face of the rear panel is incorrect (too short). You should therefore supply spacers for fitting between the inner face of the Podule backpanel and the back face of the Archimedes. 1.2.1 Fitting a Podule ---------------------- To fit or remove a Podule, the power to the machine must be turned off. The top cover must then be removed, which gives access to the Podule positions. Refer to Acorn Podule Installation Leaflet (part number 0476,201) for further information. 1.3 Types of Podule ------------------- At present there are four basic types of Podule 1 Simple Podules 2 MEMC Podules 3 Coprocessor Podules 4 External Podules 1.3.1 Simple Podules -------------------- These Podules occupy the IOC address space allocated to Podules, and are accessed via one of the four IOC cycle types. 1.3.2 MEMC Podules ------------------ These Podules attach directly to the MEMC bar IORQ/bar IOGT interface, and occupy the non-IOC address space. Each of these Podules can occupy up to 8 kbytes of address space. The cycle timing of these Podules must be determined by a state machine on the Podule. Sometimes a Podule of this category also appears as a Simple Podule, with the `Simple Podule' mapping used for control, and the `MEMC Podule' mapping used for data transfer. Care must be taken in this case as the `Simple Podule' timing is derived from CLK8 and the `MEMC Podule' timing is derived from REF8M and the phase relationship between the two clocks cannot be guaranteed. 1.3.3 Coprocessor Podules ------------------------- Coprocessor Podules share the same interface as other Podules, but they are not mapped into the I/O space as are other Podules. In addition to the normal Podule signals, coprocessors require access to the main system data bus, and extra control signals. These are provided by a special Coprocessor Podule connector, which has 96 pins. When a coprocessor is not required, this connector may be used as a normal Podule slot. Note that in this context the term `coprocessor' refers to a dedicated hardware processor, and not an additional general purpose microprocessor system. This class of Podule is only briefly referred to in this document. 1.3.4 External Podules ---------------------- Up to four Podule slots are provided in present machines. If this is insufficient, or a Podule is required to be larger than the space provided, then an external Podule (or Podules) can be fitted. One of the four normal Podule slots must be a buffer Podule to buffer all the signals on the Podule bus before they exit from the machine. External Podules can then be fitted to the buffered Podule bus. External Podules have a 32 kbyte address space allocated to them by the IOC. 2 The I/O System for ARM Based Computers ======================================== This chapter outlines the I/O system implemented on present ARM based computer systems. It is important to realise that future systems may have a different implementation of the I/O system, and in particular the addresses (and number) of Podule locations may change. For this reason, and to ensure that any device may be plugged into any slot, all driver code for Podules must be relocatable. References to the direct Podule addresses should never be used. It is up to the machine operating system, in conjunction with the Podule ID to determine the address at which a Podule should be accessed. To this extent, sections 2.1, 2.2 and 2.3 are for background information only. 2.1 System Architecture ----------------------- The I/O system (which includes Podule devices) consists of a 16 bit data bus (BD[0:15]) a buffered address bus (LA[2:21]) and various control and timing signals. The I/O data bus is independent from the main 32-bit system data bus, being separated from it by bidirectional latches and buffers. In this way the I/O data bus can run at much slower speeds than the main system bus to cater for slower peripheral devices. The latches between the two buses, and hence the I/O bus timing are controlled by the I/O controller, IOC. The IOC caters for four different cycle speeds (slow, medium, fast and synchronous) and the programmer can choose the most suitable one for each device. [Figure 1] A typical I/O system with Podules fitted is shown in figure 2. The Simple Podules are controlled by IOC, and the MEMC Podules share the I/O Controller interface with IOC. For clarity, the data and address buses are omitted from this diagram. [Figure 2] 2.1.1 non-IOC devices --------------------- The IOC is mapped to control devices in the upper half of the I/O space. The lower half of the I/O space may be used by other devices which are not mapped through, or timed by the IOC. Such devices (normally MEMC Podules) share the same handshaking control lines to the MEMC as does the IOC (the I/O Controller Interface). The advantage of devices in this class are that they are not tied to one of the four possible IOC cycle types. 2.2 System Memory Map --------------------- The system memory map is defined by the MEMC, and is shown in figure 3. Note that all system components, including I/O devices, are memory mapped. [Figure 3] 2.3 I/O Space Memory Map ------------------------ The I/O space is split into two halves, with the upper half being controlled by IOC, and the lower half allocated to non-IOC mapped devices (normally MEMC Podules). Only the lower part of the non-IOC mapped device space may be used at present. The IOC-controlled space has allocation for Simple Podules and External Podules. The MEMC Podule and Simple Podule spaces are divided into four equal parts, with one part being allocated to each physical Podule slot. Present systems may have up to four Podule slots, designated slots 0 to 3. In this way, each physical slot is identical, but each appears separately in the address space. The way in which the existence of a Podule is identified is explained in chapter 4, Podule Identity. 2.4 Podule Access Speed ----------------------- 2.4.1 Simple Podules -------------------- The Simple Podules are mapped through the IOC, and may be accessed at one of four different cycle speeds as determined by the address at which they are selected. The four cycle types are designated slow, medium, fast and synchronous. Their timings are detailed in chapter 5, Simple Podules. 2.4.2 External Podules ---------------------- External Podules are also mapped through IOC. Because of the extra buffering required, these Podules should always be accessed at the slow cycle speed. 2.4.3 MEMC Podules ------------------ The cycle timing of MEMC Podules must be driven by the Podule itself. A simple state machine clocked by the 8MHz reference signal is usually required to control these cycles. Refer to chapter 6, MEMC Podules. [Figure 4] 2.5 Podule Size --------------- The Podule Data Bus is 16 bits wide, enabling byte or half-word accesses. MEMC Podules may address 8 kbytes of data each. Simple Podules also occupy an 8 kbyte space, but some of this space is allocated to Podule identification, the exact amount being chosen by the designer. Refer to chapter 4, Podule Identity. 2.6 Data Bus Mapping -------------------- The I/O data bus is 16 bits wide. Bytewide accesses may of course be used for 8-bit peripherals. The I/O data bus (BD[0:15]) connects to the main system data bus (D[0:31]) via a set of bidirectional data latches. The mapping of the BD[0:15] bus onto the D[0:31] bus is as follows: During a WRITE (ie ARM to peripheral) BD[0:15] is mapped to D[16:31] During a READ (ie peripheral to ARM) BD[0:15] is mapped to D[0:15] 2.6.1 Byte Accesses ------------------- To access bytewide Podules, byte instructions should be used. When a byte store instruction is executed, the CPU will place the written byte on all four bytes of the word, and will therefore correctly place the desired value on the lowest byte of the I/O bus. A byte or word load may be used to read a bytewide Podule into the lowest byte of an ARM register. 2.6.2 Half-Word Accesses ------------------------ To access a 16-bit wide Podule, word instructions should be used. When storing, the half-word must be placed on the upper 16 bits, D[16:31]. To maintain upwards compatibility with future machines, half-word stores should replicate the written data on the lower half-word, D[0:15]. When reading, the upper 16 bits are undefined. 2.6.3 Word Accesses ------------------- Word-wide Podules are not currently supported by the Podule Bus. 2.7 Podule Interrupt Handling ----------------------------- There are two interrupt lines on the Podule Bus, bar PIRQ and bar PFIQ. Both lines are vectored through the IOC and generate ARM bar IRQ and bar FIQ signals respectively. bar PIRQ is the normal interrupt request line, and appears as bit 5 in the IOC IRQ Status B Register (address 3200020H). bar PFIQ is the fast interrupt request line, and appears as bit 6 in the IOC FIQ Status Register (address 3200030H). For further details on interrupt handling refer to the IOC data sheet. Note that future systems may have a different implementation of the I/O system, and in particular the addresses (and number) of Podule locations may change. A Podule generating an bar IRQ interrupt must drive the bar PIRQ line LOW. Both interrupt lines have a resistive pullup of 1k2 Ohms. In order that the ARM can determine which Podule is generating the interrupt, a Podule which is driving the bar PIRQ line LOW must also set its IRQ status bit HIGH. A Podule generating a bar FIQ interrupt must drive the bar PFIQ line LOW. In order that the ARM can determine which Podule is generating the interrupt, a Podule which is driving the bar PFIQ line LOW must also set its FIQ status bit HIGH. 2.8 Podule Identification ------------------------- It is important that the system is able to identify what Podules (if any) are present, and where they are. This is done by reading the Podule Identification (PI) byte, or bytes, from the Podule Identification Field. Refer to chapter 4, Podule Identity. 3 The Podule Bus ================ The Podule Bus is an extension of the I/O data and address buses, and carries the necessary control signals. 3.1 Simple Podule and MEMC Podule Interface ------------------------------------------- The Podule interface consists of a 64 way DIN 41612ac connector. It is defined as follows: pin a c 1 0V 0V ground 2 LA[15] -5V supply 3 LA[14] 0V ground 4 LA[13] 0V ground 5 LA[12] reserved 6 LA[11] bar MS MEMC Podule select 7 LA[10] reserved 8 LA[9] reserved 9 LA[8] reserved 10 LA[7] reserved 11 LA[6] reserved 12 LA[5] bar RST reset (see note) 13 LA[4] PR/bar W read / not write 14 LA[3] bar PWE write strobe 15 LA[2] bar PRE read strobe 16 BD[15] bar PIRQ normal interrupt 17 BD[14] bar PFIQ fast interrupt 18 BD[13] reserved 19 BD[12] C1 IIC serial bus clock 20 BD[11] C0 IIC serial bus data 21 BD[10] bar EXTPS External Podule select 22 BD[9] bar PS Simple Podule select 23 BD[8] bar IOGT MEMC Podule handshake 24 BD[7] bar IORQ MEMC Podule request 25 BD[6] bar BL I/O data latch control 26 BD[5] 0V Supply 27 BD[4] CLK2 2MHz synchronous clock 28 BD[3] CLK8 8MHz synchronous clock 29 BD[2] REF8M 8MHz reference clock 30 BD[1] +5V supply 31 BD[0] reserved 32 +5V +12V supply The reserved pins must be left unused as in some machines these pins carry coprocessor signals. Note : The bar RST signal is the system reset signal, driven by IOC on power-up or by the keyboard reset switch. It is an open-collector signal, and Podules may drive it also if this is desirable. The pulse width should be at least 50ms. 3.2 Coprocessor Podule Interface -------------------------------- The Coprocessor Podule Interface is a 96 way DIN 41612abc connector. Ivis the same as a normal Podule connector except that the b row is loaded with the main system data bus, and most of the reserved pins are allocated. pin a b c 1 0V D[0] 0V 2 LA[15] D[1] -5V 3 LA[14] D[2] 0V 4 LA[13] D[3] 0V 5 LA[12] D[4] SPVMD supervisor mode 6 LA[11] D[5] bar MS 7 LA[10] D[6] CPA coprocessor absent 8 LA[9] D[7] CPB coprocessor busy 9 LA[8] D[8] CPI coprocessor instruction 10 LA[7] D[9] OPC op-code fetch 11 LA[6] D[10] PHI2 ARM phase 2 clock 12 LA[5] D[11] bar RST 13 LA[4] D[12] PR/bar W 14 LA[3] D[13] bar PWE 15 LA[2] D[14] bar PRE 16 BD[15] D[15] bar PIRQ 17 BD[14] D[16] bar PFIQ 18 BD[13] D[17] reserved 19 BD[12] D[18] C1 20 BD[11] D[19] C0 21 BD[10] D[20] bar EXTPS 22 BD[9] D[21] bar PS 23 BD[8] D[22] bar IOGT 24 BD[7] D[23] bar IORQ 25 BD[6] D[24] bar BL 26 BD[5] D[25] 0V 27 BD[4] D[26] CLK2 28 BD[3] D[27] CLK8 29 BD[2] D[28] REF8M 30 BD[1] D[29] +5V 31 BD[0] D[30] DBE ARM data bus enable 32 +5V D[31] +12V 3.3 Main PCB Connector ---------------------- The connector fitted to the main PCB is broadly similar to the coprocessor interface without the the power pins and without the individual Podule select lines. The backplane receives 0V, +5V and +12V directly from the power supply. Several different backplanes are supported. The simplest is one which supports one or two Podules, and the most complex is one which supports four Podules one of which can be a coprocessor. In all cases the backplane generates the individual Podule select lines (bar PS and bar MS) from the master Simple Podule Select (bar S4) and MEMC Podule Select (LA[21]) lines using LA[14] and LA[15] to decode the four Podules. The Coprocessor Podule Interface, where implemented, is on Podule slot 2. The signals which are dedicated to coprocessor functions (and which are reserved on the other Podule slots) are only tracked to Podule slot 2. This includes the whole of the b row of the connector (D[0:31]). The connector on the main PCB is as follows. Note that some machines will not support the coprocessor interface, and carry a 64 way connector (b row unpopulated). pin a b c 1 0V D[0] 0V 2 LA[15] D[1] -5V 3 LA[14] D[2] 0V 4 LA[13] D[3] 0V 5 LA[12] D[4] SPVMD 6 LA[11] D[5] LA[21] 7 LA[10] D[6] CPA 8 LA[9] D[7] CPB 9 LA[8] D[8] CPI 10 LA[7] D[9] OPC 11 LA[6] D[10] PHI2 12 LA[5] D[11] bar RST 13 LA[4] D[12] PR/bar W 14 LA[3] D[13] bar PWE 15 LA[2] D[14] bar PRE 16 BD[15] D[15] bar PIRQ 17 BD[14] D[16] bar PFIQ 18 BD[13] D[17] bar S6 19 BD[12] D[18] C1 20 BD[11] D[19] C0 21 BD[10] D[20] bar EXTPS 22 BD[9] D[21] bar S4 master Podule select 23 BD[8] D[22] bar IOGT 24 BD[7] D[23] bar IORQ 25 BD[6] D[24] bar BL 26 BD[5] D[25] 0V 27 BD[4] D[26] CLK2 28 BD[3] D[27] CLK8 29 BD[2] D[28] REF8M 30 BD[1] D[29] 0V 31 BD[0] D[30] DBE 32 0V D[31] 0V 3.4 Loading of the Podule Bus ----------------------------- Each Podule may present one load to the Podule Bus signals CLK2, CLK8 and REF8M. Each Podule may present two loads to other signals on the Podule Bus, where the load may be either HC, HCT, LS, ALS or F series logic. The use of HCMOS logic is highly recommended. When driving the data bus from a Podule, care should be taken not to overdrive the bus. Series resistive termination of these lines with about 68 Ohms is recommended. 3.5 Signal Standards -------------------- All signals from the main PCB to the Podules are CMOS logic levels. Podules may drive the bus with TTL logic levels, but CMOS logic levels are recommended. 3.6 Power Requirements ---------------------- Voltages available on the Podule Connector are -5V, +5V and +12V. In normal cases Podules should take no more than the following current from any one rail: -5V 50mA +5V 1A +12V 250mA An individual Podule may in some circumstances take more than this, but this will then restrict the mixing of Podules within one machine. The total amount of power available for Podules varies with different machines in the range. Power available on the Archimedes 300 and 400 series is around 20W total but this may be reduced by the addition of other internal upgrades, such as disc drives. The use of the +12V rail and the -5V rail is not encouraged. Wherever possible only the +5V rail should be used, as future ARM based products may only have an internal +5V supply. 4 Podule Identity ================= Each Podule must be capable of identifying itself to the host operating system, and this is done by means of the Podule Identity (PI). It consists of at least one byte (the low byte) of which bits 3 to 7 carry PI information, and is usually followed by several more bytes. The PI is read by a synchronous read of address 0 of the Podule space. 4.1 Podule Identity Space ------------------------- The Podule identity space starts at Podule address 0 and extends into the Podule space as required. The minimum PI, which all Podules must support, is a single readable byte at address 0, called the PI low byte. Most Podules will support an extended PI which consists of eight bytes starting from address 0. The PI (whether extended or not) must appear at the bottom of the Podule space, from address zero upwards after reset. It does not however have to remain readable at all times, so it can be in a paged address space so long as the Podule is set to page zero on reset. Refer to sections 4.2.2 and 4.3.1. This has the effect that the PI, including the Podule present bit, is only valid after reset until the Podule driver is installed. The first 16 bytes of the Podule Identity space is assumed to be bytewide only. The space after this may be 8, 16 or, in the future, 32 bits wide. Bits 2 and 3 in byte 1 of the extended PI (W0, W1) indicate the width of the code (if any) which follows. If the PI is included in a ROM which is 16 or 32 bits wide, then only the lowest byte in each half-word or word must be used for the first 16 (half) words. 4.1.1 Code Space ---------------- In addition to the Podule identity, which all Podules must support, a Podule can contain code or data in ROM. This will typically be used for driver code for the Podule, and will be downloaded into system memory by the operating system before it is used. Often this code will be in a paged address space. The manner in which this code is accessed is variable and so it is accessed via a loader. The format of the loader is defined for each operating system, and gives access to a paged address space. The loader must live in the Podule space above the PI after reset, the position and size of it being defined by a Chunk Directory entry. Note that the PI and the loader may themselves be in the paged address space as long as they appear at address zero after reset. Refer to section 4.5. 4.2 Podule Identity Low Byte ---------------------------- The low byte of the PI is as follows : 7 6 5 4 3 2 1 0 +-----+-----+-----+-----+-----+-----+-----+-----+ | A |ID[3]|ID[2]|ID[1]|ID[0]| FIQ | P | IRQ | +-----+-----+-----+-----+-----+-----+-----+-----+ IRQ = 0 : not requesting IRQ ) see text = 1 : requesting IRQ ) P = 0 : Podule is present FIQ = 0 : not requesting FIQ ) see text = 1 : requesting FIQ ) ID[3:0] = 0 : extended PI <> 0 : ID field A = 0 : Acorn conformant Podule = 1 : non-conformant Podule 4.2.1 Podule Presence --------------------- The host operating system has to know if there are any Podules present. Normally BD[1] is pulled high by a weak pullup. Reading the low byte of the PI will therefore read a 1 on this bit unless a Podule is present. All Podules must have bit 1 LOW in the low byte of the PI. 4.2.2 Podule Interrupts ----------------------- A Podule which is capable of generating a bar PIRQ or a bar PFIQ MUST carry a status bit for each of these interrupt sources. These 2 status bits must be in the low byte of the PI unless the Podule contains an extended PI in which case the status bits may be relocated in the Podule address space. Refer to section 4.3.1. A Podule which is holding bar PIRQ LOW must set bit 0 HIGH in the low byte of the PI. A Podule which is holding bar PFIQ LOW must set bit 2 HIGH in the low byte of the PI. In this way the operating sytem can quickly find which Podule is generating the interrupt. If the Podule contains paged ROM, these status bits may be located elsewhere in the Podule address space, in which case the 2 bits in the PI low byte should be zeros. The location of these status bits must appear in the ROM space above the extended PI. See section 4.4. If a Podule is not capable of generating either a bar PIRQ or a bar PFIQ then bits 0 and/or 2 in the low byte PI must be zero. If the interrupt status bits have been relocated, then the respective position mask should be set to zero. Refer to section 4.4 4.2.3 ID field -------------- There are 4 bits in the low byte of the PI (BD[3:6]) which may be used for Podule identification. These should only be used for the very simplest of Podules or temporarily during development. Most Podules should implement the extended PI which eliminates the possibility of Podule IDs clashing. When an extended PI is used, all four bits in the ID field of the low byte PI must be zero. 4.2.4 Acorn Discriminator ------------------------- The most significant bit in the low byte of the PI must be zero for Podules that conform to this Acorn specification. 4.3 Identification Extension ---------------------------- If the ID field of the low byte of the PI is zero then the PI is extended. This means that the next seven bytes of the PI will be read by the operating system. The extended PI starts at the bottom of page 0 of the paged identity space, and consists of eight bytes as defined below. If bit 0 of byte 1 is not set then the extended PI is just eight bytes long. If bit 0 of byte 1 (CD) is set, then a Chunk Directory follows the Interrupt Status Pointers. 7 6 5 4 3 2 1 0 +-----+-----+-----+-----+-----+-----+-----+-----+ | C[7]| C[6]| C[5]| C[4]| C[3]| C[2]| C[1]| C[0]| 1CH +-----+-----+-----+-----+-----+-----+-----+-----+ |M[15]|M[14]|M[13]|M[12]|M[11]|M[10]| M[9]| M[8]| 18H +-----+-----+-----+-----+-----+-----+-----+-----+ | M[7]| M[6]| M[5]| M[4]| M[3]| M[2]| M[1]| M[0]| 14H +-----+-----+-----+-----+-----+-----+-----+-----+ |P[15]|P[14]|P[13]|P[12]|P[11]|P[10]| P[9]| P[8]| 10H +-----+-----+-----+-----+-----+-----+-----+-----+ | P[7]| P[6]| P[5]| P[4]| P[3]| P[2]| P[1]| P[0]| 0CH +-----+-----+-----+-----+-----+-----+-----+-----+ | R | R | R | R | R | R | R | R | 08H +-----+-----+-----+-----+-----+-----+-----+-----+ | R | R | R | R | W[1]| W[0]| IS | CD | 04H +-----+-----+-----+-----+-----+-----+-----+-----+ | A | 0 | 0 | 0 | 0 | F | 0 | I | 00H <- Page zero +-----+-----+-----+-----+-----+-----+-----+-----+ A = 0 : Acorn conformant Podule = 1 : non-conformant Podule F = 0 : not requesting FIQ ) see text = 1 : requesting FIQ ) I = 0 : not requesting IRQ ) see text = 1 : requesting IRQ ) R = 0 : mandatory at present = 1 : reserved for future use CD = 0 : no Chunk Directory follows = 1 : Chunk Directory follows Interrupt Status Pointers IS = 0 : Interrupt Status appears in low byte PI = 1 : Interrupt Status has been relocated W[1:0] = 0 : 8-bit code follows after byte 15 of ID = 1 : 16-bit code follows after byte 15 of ID = 2 : 32-bit code follows after byte 15 of ID = 3 : reserved C[7:0] = : Country M[15:0] = : Manufacturer P[15:0] = : Product Type 4.3.1 FIQ and IRQ Status ------------------------ If bit 1 in byte 1 of the extended PI (IS) is not set, then the interrupt status bits have not been relocated within the Podule address space. In this case the FIQ and IRQ status bits must appear as bits 2 and 0 respectively in the low byte of the PI. Podules which cannot generate interrupts must drive these bits to zero. If bit 0 in byte 1 of the extended PI (CD) is not set either, then the Interrupt Status Pointers do not need to be defined, as the operating system will not read them. If CD is set, then the Interrupt Status Pointers should be defined to point to the respective bits in the PI low byte. If bit 1 of byte 1 of the extended PI (IS) is set, then the interrupt status bits have been relocated within the Podule space. In this case the Interrupt Status Pointers must be defined as described in section 4.4 Note that if both IRQ and FIQ sources are provided by a Podule, then a separate status bit must exist for each type of interrupt source, though the two status bits may appear at the same address if convenient. Refer to section 4.4. 4.3.2 Country Code ------------------ Every Podule should have a code for the country of origin. The current allocation of country codes is as follows: Country name Code Value UK 0 Italy 4 Spain 5 France 6 Germany 7 Portugal 8 Greece 10 Sweden 11 Finland 12 Denmark 14 Norway 15 Iceland 16 Canada 17 Turkey 20 Consult Acorn for further allocation of codes. 4.3.3 Manufacturer Code ----------------------- Every Podule should have a code for manufacturer. The current allocation of manufacturer codes is as follows: Manufacturer Code Value Acorn UK 0 Acorn USA 1 Olivetti 2 Watford 3 Computer Concepts 4 Intelligent Interfaces 5 Caman Systems 6 Armadillo 7 Soft Option 8 Wild Vision 9 Anglo Computers 10 Resource 11 Allied Interactive 12 Musbury Consultants 13 Consult Acorn for further allocation of codes. 4.3.4 Product Type Code ----------------------- Every Podule type must have a unique number allocated to it. The current allocation of Podule type codes is as follows: Product type Code Value Host Tube 0 Parasite Tube 1 SCSI 2 Ethernet 3 IBM Disc 4 RAM/ROM 5 BBC IO 6 Modem 7 Teletext 8 CDROM 9 IEEE 488 10 Hard Disc 11 ESDI 12 SMD 13 Laser Printer 14 Scanner 15 Fast Ring 16 VME Bus 17 PROM Programmer 18 MIDI 19 Mono VPU 20 Frame Grabber 21 Sound Sampler 22 Video Digitiser 23 GenLock 24 CODEC Sampler 25 Image Analyser 26 Analogue Input 27 CD Sound Sampler 28 6 MIPS Signal Processor 29 12 MIPS Signal Processor 30 33 MIPS Signal Processor 31 Touch Screen 32 Transputer Link 33 Interactive Video 34 Consult Acorn for further allocation of codes. 4.4 Interrupt Status Pointers ----------------------------- If bit 1 of byte 1 of the extended PI (IS) is set, then the address of the FIQ and IRQ status bits must be provided in the eight bytes which follow the extended PI, even if the two status bits are at address 0. There are two sets of 4-byte numbers as detailed below, each consisting of a 3-byte address field and a 1-byte position mask field. The position mask defines which bit within the status byte refers to the status bit. It should consist of 1 `one' and 7 `zeros'. The other bits within the status byte may be `don't cares'. If the Podule does not provide one of these interrupt sources, then the respective position mask should consist of 8 `zeros'. If bit 0 of byte 1 of the extended PI (CD) is set, then bit 1 of byte 1 of the extended PI (IS) must be set and hence the addresses must be present. Note that these eight bytes are always assumed to be bytewide. Only the lowest byte in each word should be used. After byte 15 (address 40H upwards), wider words may be used, according to the setting of W[1] and W[0] in the extended ID. See section 4.3 The 24-bit address field allows for an absolute byte address with an offset from 3000000H to be defined. Hence the cycle speed to access the status register can be included in the address (encoded by bits 19 and 20). Bits 14 and 15 should be zero. +-------------------+ 40H | IRQ Status Bit | | Address (24 bits) | +-------------------+ 34H | IRQ Status Bit | | Position Mask | +-------------------+ 30H | FIQ Status Bit | | Address (24 bits) | +-------------------+ 24H | FIQ Status Bit | | Position Mask | +-------------------+ 20H 4.5 Chunk Directory Structure ----------------------------- If bit 0 of byte 1 of the extended PI (CD) is set, then following the Interrupt Status Pointers is a directory of chunks of data and/or code stored in the ROM. The lengths and types of these chunks and the manner in which they are loaded is variable, so after the eight bytes of Interrupt Status Pointers there follow a number of entries in the Chunk Directory. The Chunk Directory entries are eight bytes long and all follow the same format. There may be any number of these entries. This list of entries is terminated by a block of four bytes of zeros. Note that from here on the definition is in terms of bytes. If the Podule supports a 16 (or in the future 32 bit) wide interface then the operating system must take this into account. +-------------------+ n+8 | Start address | | 4 Bytes (32 bits) | +-------------------+ n+4 | Size in bytes : | 3 Bytes (24 bits) | +-------------------+ n+1 | Operating System | | Identity Byte | +-------------------+ n One of these blocks must be the Code Loader. It contains the code to load bytes from the (paged) ROM into main memory, and as such is capable of updating the page register as required. There may be more than one loader present, to cater for different operating systems. All the loader code must be accessible after reset. After the loader is transferred to main memory, all further chunks are transferred via the loader. The chunks are again referenced by Chunk Directory as above, starting at a virtual address of zero. Note that after the loader has been loaded, the main Podule ID area may be mapped out. An example of a typical use of the Chunk Directory is shown in figure 5. The shaded areas refer to chunks which are transferred via the loader. [Figure 5] 4.5.1 Operating System Identity Byte ------------------------------------ The Operating System Identity Byte forms the first byte of the Chunk Directrory entry, and determines the type of data which appears in the chunk to which the Chunk Directory refers. It is defined as follows. 7 6 5 4 3 2 1 0 +-----+-----+-----+-----+-----+-----+-----+-----+ |OS[3]|OS[2]|OS[1]|OS[0]| D[3]| D[2]| D[1]| D[0]| +-----+-----+-----+-----+-----+-----+-----+-----+ OS[3] = 0 reserved OS[3] = 1 mandatory at present OS[2:0] = 0 Acorn Operating System #0 Arthur D[3:0] = 0 loader 1-15 operating system dependent 1 Acorn Operating System #1 D[3:0] = 0 loader 1-15 reserved 2 Acorn Operating System #2 D[3:0] = 0 loader 1-15 reserved 3-5 reserved D[3:0] = 0-15 reserved 6 manufacturer defined D[3:0] = 0-15 manufacturer specific 7 device data D[3:0] = 0 link (for 0, the object pointed to is another directory) 1 serial number 2 date of manufacture 3 modification status 4 place of manufacture 5 description 6 part number (for 1-6, the data in the pointed-to location contains the ASCII string of the information.) 7-15 reserved 4.6 Examples of Use ------------------- The previous paragraphs explain the system of Podule identification. You do not need to use all of these features on all Podules, and the implementation depends on the needs and complexity of the Podule in question. All Podules must implement at least the simplest form of Podule identification. Synchronous cycles are used by the operating system to read and write any locations within the PI space (to simplify the design of sysnchronous Podules). 4.6.1 Non-extended Podule Identity ---------------------------------- This is the simplest possible Podule identity mechanism. It may be used for temporary Podules or where Podules are used in a localised, closed environment. It should not be used for Podules for general sale. Non-extended PIs do not need R/W factored into their enable, as the operating system will only read the PI space. [Figure 6] 4.6.2 Extended Podule Identity ------------------------------ The next simplest case which most Podules should implement as a minimum is the case of an extended PI but no code in ROM. This can be achieved by a 32 X 8 bit PROM. An example is shown in figure 7. [Figure 7] 4.6.3 Extended PI with paged ROM -------------------------------- When the Podule includes driver code in ROM, there are several possibilities for implementing the PI. One example showing an EPROM with a paging register is shown in figure 8. Simplifications can be made where there is only one page, or where a larger EPROM allows the inclusion of the low byte of the PI. (FIQ and/or IRQ can be factored into the address space as in the previous example). [Figure 8] 5 Simple Podules ================ Simple Podules are controlled by the IOC. These Podules may be accessed by one of four types of cycle, designated slow, medium, fast, and synchronous. The cycles are mapped at different addresses as described in section 2.4. Once the cycle has started, MEMC may deassert bar IORQ (and hence IOC will deassert bar RBE) in order to carry out memory refresh or DMA operations. This is indicated by the shaded area in figure 9. If, when the IOC has finished the cycle, the MEMC has not reasserted bar IORQ then the I/O cycle will be stretched until the MEMC is ready to complete the cycle. This does not however alter the cycle the Podule sees, because the cycle is in effect finished before the stretching takes place: in the case of a write the bar WBE and bar PS have already been deasserted, and in the case of a read the data from the Podule has already been latched into the data buffers by bar BL Figure 9 shows how the IOC generates a fast Podule read: the IOC generates the Podule read, write and select strobes, and also controls the bar IOGT and bar BL signals. The Podule read, write and select signals are timed with respect to the signal CLK8 and NO relationship between REF8M and CLK8 can be assumed. [Figure 9 - IOC Driving a Podule Read Cycle] Note : shaded areas; refer to text above. Figure 10 shows the same cycle, but this time the MEMC has deasserted bar IORQ at the time when the IOC is about to finish the cycle. Accordingly, the cycle is stretched by one 8MHz clock period (the shaded region), but note that the access to the Podule has not been stretched. [Figure 10 - Stretched Podule Read Cycle] 5.1 Podule Accesses ------------------- The following diagrams detail the four possible types of IOC Podule access. In each diagram REF8M is shown, but this is only for reference. The phase relationship of REF8M and CLK8 is NOT guaranteed. 5.1.1 slow cycle read --------------------- [Figure 11] 5.1.2 slow cycle write ---------------------- [Figure 12] 5.1.3 medium cycle read ----------------------- [Figure 13] 5.1.4 medium cycle write ------------------------ [Figure 14] 5.1.5 fast cycle read --------------------- [Figure 15] 5.1.6 fast cycle write ---------------------- [Figure 16] 5.2 General Timing For Slow, Medium and Fast Cycle Types -------------------------------------------------------- [Figure 17] Note : REF8M is shown here for reference only. Do not assume any phase relationship between REF8M and CLK8. _____________________________________________________________________ | | | | | | | | | Sym | Parameter | Min | Nom | Max | Units | Note | |_____|______________________________|_____|_____|_____|_______|______| | | __ | | | | | | | t1 | PS setup to CLK8 | 40 | | 120 | ns | | | | __ | | | | | | | t2 | PS width TYPE slow | | 625 | | ns | | | | __ | | | | | | | t2 | PS width TYPE med | | 500 | | ns | | | | __ | | | | | | | t2 | PS width TYPE fast | | 375 | | ns | | | | __ | | | | | | | t3 | PS hold from CLK8 | 0 | | 50 | ns | | | | __ ___ ___ | | | | | | | t4 | PS to PRE/PWE TYPE slow | | 187 | | ns | | | | | | | | | | | t4 | PS to PRE/PWE TYPE med/fast| | 62 | | ns | | | | ___ ___ | | | | | | | t5 | PRE/PWE delay from CLK8 | 0 | | 15 | ns | | | | ___ ___ | | | | | | | t6 | PRE/PWE width TYPE slow/med| | 375 | | ns | | | | ___ ___ | | | | | | | t6 | PRE/PWE width TYPE fast | | 250 | | ns | | | | | | | | | | | t7 | write data setup to CLK8 | 100 | | | ns | | | | ___ | | | | | | | t8 | read data setup to PRE | 20 | | | ns | | | | ___ | | | | | | | t9 | read data hold from PRE | 15 | | | ns | | | | | | | | | | | t10 | address setup to CLK8 | 150 | | | ns | | | | _ | | | | | | | t11 | PR/W setup to CLK8 | 140 | | | ns | | |_____|______________________________|_____|_____|_____|_______|______| 5.3 synchronous cycle read -------------------------- [Figure 18] Note : (A) (B) (C), (D) refer to the 4 possible cases to allow for synchronisation to the CLK2 signal. 5.4 synchronous cycle write --------------------------- [Figure 19] 5.5 Timings for Synchronous Cycle Type -------------------------------------- [Figure 20] _____________________________________________________________________ | | | | | | | | | Sym | Parameter | Min | Nom | Max | Units | Note | |_____|______________________________|_____|_____|_____|_______|______| | | | | | | | | | t12 | CLK2 delay from CLK8 | 0 | | 15 | ns | | | | __ | | | | | | | t13 | PS delay from CLK8 | 5 | | 50 | ns | | | | __ | | | | | | | t14 | PS hold from CLK8 | 10 | | | ns | | | | ___ ___ | | | | | | | t15 | PRE/PWE delay from CLK8 | 0 | | 15 | ns | | | | __ | | | | | | | t16 | write data setup to PS | 100 | | | ns | | | | ___ | | | | | | | t16a| write data hold from PWE/CLK2| 20 | | | ns | | | | ___ | | | | | | | t17 | read data setup to PRE/CLK2 | 50 | | | ns | | | | ___ | | | | | | | t18 | read data hold from PRE/CLK2| 15 | | | ns | | | | __ | | | | | | | t19 | address setup to PS | 150 | | | ns | | | | ___ ___ | | | | | | | t20 | add. hold from PRE/PWE/CLK2 | 10 | | | ns | | | | _ __ | | | | | | | t21 | PR/W setup to PS | 140 | | | ns | | | | _ ___ ___ | | | | | | | t22 | PR/W hold from PRE/PWE/CLK2 | 10 | | | ns | | | | | | | | | | | t23 | cycle time square wave | | 500 | | ns | | |_____|______________________________|_____|_____|_____|_______|______| 6 MEMC Podules ============== MEMC Podules are not controlled by IOC. They share the same interface with MEMC as does the IOC, and therefore have to time their own cycles, by their I/O controller. This interface has two control lines, bar IORQ (driven by MEMC) and bar IOGT (driven by the Podule or IOC). bar IOGT is an open drain signal allowing multiple devices to sit on this interface. MEMC Podules are decoded by LA[21] LOW, and IOC is decoded by LA[21] HIGH. But even when IOC is not selected, it continues to control the external buffer enables, bar RBE and bar WBE. The latching of the buffer must however be controlled by the Podule which is controlling the cycle. This is done by pulling bar BL LOW, and is also an open drain signal. 6.1 I/O Controller Interface ---------------------------- I/O Controllers use a handshaking system to synchronise I/O peripherals with the system data bus. The interface is timed with respect to the REF8M clock, and cycles may be produced in multiples of 8MHz clock `ticks'. When the processor accesses the I/O Controller address space (while MEMC is in Supervisor mode), MEMC starts an I/O cycle by driving bar IORQ LOW and holding the processor clocks (stretching the processor cycle when PH2 is HIGH). The I/O Controller signals that it is ready to end the I/O cycle by driving bar IOGT LOW. The I/O cycle terminates after both bar IORQ and bar IOGT are seen LOW on the rising edge of REF8M, with MEMC driving bar IORQ HIGH and releasing the processor clocks, and the I/O Controller driving bar IOGT HIGH on the next falling edge of REF8M. An I/O cycle is shown in figure 21. The cycle starts with bar IORQ being taken low. There then follow a number of 8MHz clock ticks until the I/O Controller is in a position to complete the cycle. The bar IOGT line is taken low, and both MEMC and the I/O controller see bar IORQ and bar IOGT LOW on the rising edge of REF8M, so the I/O cycle terminates on the next falling edge of REF8M. [Figure 21 - I/O Cycle] Some I/O cycles may only take 250ns as shown in figure 22. To give the I/O Controller adequate time to recognise such operations, MEMC produces the first bar IORQ early in the I/O cycle. The extension of bar IORQ only happens at the start of an I/O cycle; if the bar IORQ signal is removed during a DMA or refresh operation, it will be reasserted when REF8M goes LOW. [Figure 22 - Fast I/O cycle] I/O cycles may be interrupted by DMA and refresh operations, as shown in figure 23. If a DMA or refresh operation is pending, the bar IORQ signal is driven HIGH when REF8M next goes LOW. The DMA/refresh operation may then begin, and when it completes, the I/O cycle is resumed by setting bar IORQ LOW (provided no more DMA or refresh operations are pending). The DBE line is always driven LOW during DMA/refresh operations to disable the processor data bus drivers. Hence the I/O cycle is stretched, and the write data would become invalid in the middle of the cycle. The data must therefore be latched into the data bus buffers by the I/O controller during the first bar IORQ LOW period, and be held until the I/O cycle has completed. This is done by the I/O controller driving bar BL LOW for this period. The maximum time for which an I/O cycle may be interrupted in this way is 1875ns (ie fifteen 8MHz cycles). [Figure 23 - I/O Cycle interrupted by a DMA or refresh operation] NOTE: Care must be taken not to address a non-existent I/O Controller, as MEMC will hold the processor clocks indefinitely until a LOW is seen on the bar IOGT line, or RESET is set HIGH. 6.2 MEMC Podule Timing ---------------------- A typical cycle with timing parameters is shown in figure 24. The sequence consists of a MEMC Podule access, a DRAM refresh by MEMC, with the end of the Podule access delayed by one 8MHz clock cycle. [Figure 24] _____________________________________________________________________ | | | | | | | | | Sym | Parameter | Min | Nom | Max | Units | Note | |_____|______________________________|_____|_____|_____|_______|______| | | ____ | | | | | | | t24 | IORQ setup (first attempt) | 70 | | 115 | ns | | | | ____ | | | | | | | t25 | IORQ setup (retries) | 50 | | 75 | ns | | | | ____ | | | | | | | t26 | IORQ hold | 50 | | | ns | | | | ____ | | | | | | | t27 | IOGT setup | 25 | | 120 | ns | | | | ____ | | | | | | | t28 | IOGT hold | 10 | | 100 | ns | | | | __ | | | | | | | t29 | MS setup to REF8M | 110 | | | ns | | | | __ | | | | | | | t30 | MS hold | 5 | | | ns | | | | __ | | | | | | | t31 | BL delay write| 0 | | 65 | ns | | | | __ | | | | | | | t32 | BL hold read | 10 | | 100 | ns | | | | | | | | | | | t33 | BD[0:15] setup write| 85 | | | ns | 1 | | | __ | | | | | | | t34 | BD[0:15] hold from BL write| 5 | | | ns | | | | | | | | | | | t35 | BD[0:15] setup to REF8M read| 50 | | | ns | 2 | | | __ | | | | | | | t36 | BD[0:15] setup to BL read| 20 | | | ns | | | | __ | | | | | | | t37 | BD[0:15] hold from BL read| 15 | | | ns | | | | _ | | | | | | | t38 | LA[2:15], PR/W setup to REF8M| 140 | | | ns | | |_____|______________________________|_____|_____|_____|_______|______| __ Note 1 : with BL HIGH ie. buffers transparent. Note 2 : setup to the earliest possible end of cycle. ÿ