----------------------------------------------- A R C H I M E D E S M E M O R Y M A P ----------------------------------------------- !!! To Access Hardware Addresses, Enter Supervisor Mode !!! ----------------- ---------------------------------------- Hex Address Description ----------------- ---------------------------------------- 0000000 - 1FFFFFF Logically Mapped RAM (Read/Write) 0000000 - 0000003 Reset Vector 0000004 - 0000007 Undefined Instruction Vector 0000008 - 000000B Software Interrupt Vector 000000C - 000000F Abort (Prefetch) Vector 0000010 - 0000013 Abort (Data) Vector 0000014 - 0000017 Address Exception Vector 0000018 - 000001B IRQ Vector 000001C - 000001F FIRQ Vector 2000000 - 2FFFFFF Physically Mapped RAM (Read/Write) 3000000 - 33FFFFF Input/Output Conntrollers (Read/Write) -------- ----------------------------------------------------- Register Register Function -------- ----------------------------------------------------- Read Write ------------------- -------------------------------- 00 Control Register Control Register 04 Serial Rx Data Serial Tx Data 08 - - 0C - - 10 IRQ Status A - 14 IRQ Request A IRQ Clear 18 IRQ Mask A IRQ Mask A 1C - - 20 IRQ Status B - 24 IRQ Request B - 28 IRQ Mask B IRQ Mask B 2C - - 30 FIRQ Status - 34 FIRQ Request - 38 FIRQ Mask FIRQ Mask 3C - - 40 Timer 0 Count Low Timer 0 Latch Low ....Tinterval=latch/2 microsecs (RCLK 8 MHz) 44 Timer 0 Count High Timer 0 Latch High 48 - Timer 0 Go Command 4C - Timer 0 Latch Command 50 Timer 1 Count Low Timer 1 Latch Low ....Tinterval=latch/2 microsecs (RCLK 8 MHz) 54 Timer 1 Count High Timer 1 Latch High 58 - Timer 1 Go Command 5C - Timer 1 Latch Command 60 Timer 2 Count Low Timer 2 Latch Low ....(BAUD) BAUD rate=1/(latch+1) MHz 64 Timer 2 Count High Timer 2 Latch High (500 KHz Maximum) 68 - Timer 2 Go Command 6C - Timer 2 Latch Command 70 Timer 3 Count Low Timer 3 Latch Low ....(KART) BAUD rate=1/((latch+1)*16) MHz 74 Timer 3 Count High Timer 3 Latch High (31250 Hz Maximum) 78 - Timer 3 Go Command 7C - Timer 3 Latch Command -------- ------------------- -------------------------------- 3290000 - VL1772 Floppy Disc Controller 3400000 - 37FFFFF Low ROM (4M bytes Read Only) 3800000 - 3FFFFFF High ROM (8M bytes Read Only) 3400000 - 35FFFFF Video Controller (Write Only) -------- ------------------------------------ ------------------------------------------- Register Register Function Requirements -------- ------------------------------------ ------------------------------------------- 00 Video Palette Logical Colour 0 - 04 Video Palette Logical Colour 1 - 08 Video Palette Logical Colour 2 - 0C Video Palette Logical Colour 3 - 10 Video Palette Logical Colour 4 - 14 Video Palette Logical Colour 5 - 18 Video Palette Logical Colour 6 - 1C Video Palette Logical Colour 7 - 20 Video Palette Logical Colour 8 - 24 Video Palette Logical Colour 9 - 28 Video Palette Logical Colour A - 2C Video Palette Logical Colour B - 30 Video Palette Logical Colour C - 34 Video Palette Logical Colour D - 38 Video Palette Logical Colour E - 3C Video Palette Logical Colour F - 40 Border Colour Register - 44 Cursor Palette Logical Colour 1 - 48 Cursor Palette Logical Colour 2 - 4C Cursor Palette Logical Colour 3 - 50 Reserved - 54 Reserved - 58 Reserved - 5C Reserved - 60 Stereo Image Register 7 - 64 Stereo Image Register 0 - 68 Stereo Image Register 1 - 6C Stereo Image Register 2 - 70 Stereo Image Register 3 - 74 Stereo Image Register 4 - 78 Stereo Image Register 5 - 7C Stereo Image Register 6 - 80 Horizontal Cycle Register HCR=(N-2)/2, where N must be even 84 Horizontal Sync Width Register HSWR=(N-2)/2, where N must be even 88 Horizontal Border Start Register HBSR=(M-1)/2, where M must be odd 8C Horizontal Display Start Register HDSR=(M-5)/2, for 8 bits per pixels mode HDSR=(M-7)/2, for 4 bits per pixels mode HDSR=(M-11)/2, for 2 bits per pixels mode HDSR=(M-19)/2, for 1 bits per pixels mode 90 Horizontal Display End Register HDER is the same as HDSR 94 Horizontal Border End Register HBER=(M-1)/2, where M must be odd 98 Horizontal Cursor Start Register HCSR=(M-6), where M must be odd 9C Horizontal Interlace Register HIR=(L+1)/2, where L must be odd A0 Vertical Cycle Register VCR=(N-1) or VCR=(N-3)/2 if interlace is used, N is odd A4 Vertical Sync Width Register VSWR=(N-1) A8 Vertical Border Start Register VBSR=(N-1) AC Vertical Display Start Register VDSR=(N-1) ....N is the number of rasters required B0 Vertical Display End Register VDER=(N-1) in all cases! B4 Vertical Border End Register VBER=(N-1) B8 Vertical Cursor Start Register VBER=(N-1) BC Vertical Cursor End Register VBER=(N-1) C0 Sound Frequency Register SFR=(N-1) ....N=sample period in microsecs C4-DC Reserved - E0 Control Register - E4-FC Reserved - -------- ------------------------------------ ------------------------------------------- 3600000 - 37FFFFF DMA Address Generators and Control Register (Write Only) 3800000 - 3FFFFFF Logical-to-Physical Address Translator (Write Only)